5T SRAM Cell with Improved Read/Write-ability and Reduced Standby Leakage Current
نویسندگان
چکیده
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist circuitries is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to a power supply voltage VDD such that the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, introducing a two-stage reading mechanism to increase the reading speed and thus to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby.
منابع مشابه
Design of High Performance Single-Port 5T SRAM Cell with Reduced Leakage Current
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